Silicon carbide (SiC) as a high performance semiconductor material, because of its excellent physical and chemical properties, in power electronics, radio frequency microwave, optoelectronics and other fields show great application potential. However, the high hardness and stable lattice structure of silicon carbide pose great challenges to its polishing process. This article will focus on the reasons for the difficulty of polishing silicon carbide substrate, in order to provide reference for the research and application in related fields.

 

 

First, high hardness and brittleness caused by polishing problems

The ultra-high hardness of silicon carbide is one of its remarkable characteristics, and the Mohs hardness is up to 9.5, second only to diamond. This high hardness characteristic makes it necessary to use equally high hardness abrasives and tools in the polishing process. However, high hardness abrasives often lead to rapid wear of polishing tools during the polishing process, which not only reduces the polishing efficiency, but also may lead to a decline in polishing quality. In addition, the brittleness of silicon carbide is also a major problem in the polishing process. In the polishing process, SiC substrate is prone to cracking, forming surface damage and cracks, these defects not only affect the appearance quality of the wafer, but also may affect its electrical performance and reliability.

 

Second, the polishing challenge brought by the stable lattice structure

The lattice structure of SiC is composed of Si-C tetrahedrons, which has a close packed structure and high stability. This stable lattice structure makes it extremely difficult to change the surface structure by external machining means. In the polishing process, to break the covalent bond between Si-C atoms, to achieve material removal and surface quality improvement, it needs to consume a lot of heat energy and friction shear force. This not only increases the energy consumption and time cost of the polishing process, but also may cause damage to the internal structure of the chip.

 

Third, the impact of stress in the polishing process

In the traditional polishing process, the workpiece and the polishing die are usually fixed by bonding glue. However, due to the inconsistent coefficient of thermal expansion between the SiC substrate and the polishing die, stress will occur at the bonding site after cooling and curing. These stresses will adversely affect the shape and finish of the wafer surface during polishing, resulting in a decline in polishing quality. In addition, the friction heat and mechanical stress generated during the polishing process can further exacerbate this effect, making the polishing process more difficult to control.

 

Fourth, the selection of polishing fluid and polishing pad

Polishing fluid and polishing pad are the key elements in the polishing process, and their selection directly affects the polishing effect. For silicon carbide substrates, because of its high hardness and brittleness, the traditional polishing fluid and polishing pad are often difficult to meet its polishing requirements. On the one hand, the composition of the polishing liquid, the particle size and the concentration of the abrasive need to be precisely controlled to avoid excessive damage to the chip; On the other hand, the hardness, elasticity and surface topography of the polishing pad also need to match the characteristics of the silicon carbide substrate to achieve the best polishing effect. However, special polishing fluids and polishing pads for SiC substrates are still scarce on the market, which further increases the difficulty and cost of the polishing process.

 

In summary, the reasons for the difficulty of polishing silicon carbide substrates mainly include its high hardness and brittleness, stable lattice structure, the influence of stress in the polishing process, and the selection of polishing fluid and polishing pad. These challenges not only affect the polishing efficiency and quality of SiC substrates, but also limit its application and development in related fields. Therefore, it is necessary to strengthen the research and innovation of silicon carbide substrate polishing technology in the future to overcome these problems and promote the wide application and development of silicon carbide materials.

Silicon carbide substrate, as a new generation of semiconductor products, has shown great application potential in the field of power electronic devices because of its excellent physical and chemical properties. However, high efficiency and low loss cutting of SiC ingot is one of the key technologies restricting its mass production. At present, mortar wire cutting and diamond wire cutting are the two mainstream technologies in SiC ingot cutting, and they have significant differences in the ways of abrasive introduction, processing efficiency, material loss and environmental impact. This article aims to compare and analyze the characteristics of these two cutting technologies, and discuss the optimization direction of SiC cutting process.

 

 

1. Abrasive import mode and processing efficiency

· mortar wire cutting: using free abrasive, the processing speed is relatively slow.

· diamond wire cutting: through electroplating, resin bonding and other methods to fix the abrasive particles, cutting speed increased by more than 5 times, significantly improve production efficiency.

2. Material loss and film output rate

· mortar wire cutting: low output rate, large material loss.

· diamond wire cutting: the output rate is increased by 15% to 20%, the material loss is significantly reduced, and the economic benefit is improved.

3. Environmental protection advantages

· Diamond wire cutting: Less waste and wastewater production, more environmentally friendly.

4. Technical challenges and coping strategies

· Diamond wire cutting: There are challenges in crystal control and cutting loss control.

· Coping strategy: The current industry adopts the strategy of mortar wire cutting as the main and diamond wire cutting as the auxiliary, the use ratio is about 5:1. In the future, it is necessary to further optimize the diamond wire cutting technology to improve its competitiveness in SiC cutting.

5. Processing loss analysis of SiC materials

· mortar wire cutting loss:

· Notch loss: up to 150-200 microns.

· Polishing loss: Surface damage needs to be repaired by rough grinding, fine grinding and CMP processes.

· back thinning loss: The initial thickness setting is high, the back thinning is required to reduce resistance.

 

 SiC cutting loss and damage

 

In summary, the diamond wire cutting technology in the cutting of SiC ingot shows significant processing speed advantages, lower material loss and environmental protection advantages, but its crystal control and cutting loss control still need to be further optimized. At present, the complementary use strategy of mortar wire cutting and diamond wire cutting is a common practice in the industry. In the future, with the continuous progress of diamond wire cutting technology and the reduction of costs, it is expected to occupy a dominant position in the SiC cutting field. At the same time, in view of the loss problem in the processing of SiC materials, it is necessary to further explore more efficient and low-loss cutting and polishing processes to promote the efficient and low-cost production of SiC semiconductor materials and promote its wide application in the field of power electronic devices.